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  <div class="section" id="fe310-g00-pll">
<h1>FE310-G00 PLL<a class="headerlink" href="#fe310-g00-pll" title="Permalink to this headline">¶</a></h1>
<p>On targets with a PLL compatible with the FE310-G000 SoC, the PLL is configured
at program initialization with a constructor. This PLL sets the clock frequency
of the RISC-V CPU, and users of Freedom Metal who wish to set a specific clock
rate can use Freedom Metal to request that the PLL take on a certain output rate.</p>
<p>In the DeviceTree for your target, there should be a node like the following
(example taken from the SiFive HiFive1):</p>
<div class="highlight-DeviceTree notranslate"><div class="highlight"><pre><span></span>hfclk: clock@4 {
        compatible = &quot;sifive,fe310-g000,pll&quot;;
        clocks = &lt;&amp;hfxoscout &amp;hfroscout&gt;;
        clock-names = &quot;pllref&quot;, &quot;pllsel0&quot;;
        reg = &lt;&amp;prci 0x8 &amp;prci 0xc&gt;;
        reg-names = &quot;config&quot;, &quot;divider&quot;;
        clock-frequency = &lt;16000000&gt;;
};
</pre></div>
</div>
<p>The <code class="docutils literal notranslate"><span class="pre">clock-frequency</span></code> property of the node sets the requested clock rate of
the FE310-G000 PLL. The PLL driver will attempt to configure the PLL to achieve
this clock rate.</p>
<p>Users should note that the FE310-G000 PLL only supports certain input/output
clock rate ratios, and so the effective output rate of the PLL may differ from
the requested rate.</p>
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